Data Integrity (NAND-level)

Maintaining Data Accuracy & Quality Over Extended Use

NAND level data integrity technologiesNAND level data integrity technologies
Firmware-Based Data-At-Rest Power Loss  Protection
Firmware-Based Data-At-Rest Power Loss Protection
The firmware-based power failure protection effectively protects data written to the device prior to power loss. After the host receives a signal from the device that the WRITE operation has been successfully completed, newly written as well as previously written data are protected even if a sudden power loss occurs.
Hardware-Based In-Flight-Data Power Loss Protection
Hardware-Based In-Flight-Data Power Loss Protection
This hardware-based power failure protection prevents data loss during a power loss event by ensuring that the last read/write/erase command is completed and data is stored safely in non-volatile flash memory. Select NVMe modules and SATA SSDs feature a new microcontroller unit (MCU)-based design that allows the PLP array to perform intelligently in various temperatures, power glitches and charge states to protect both device and data.
Advanced Wear Leveling
Advanced Wear Leveling
Manages the reads and writes across blocks evenly to optimize the overall life expectancy of a flash product
AutoRefresh
AutoRefresh
Monitors the error bit level in every operation. Before the error bit in a block reaches or exceeds the preset threshold value, AutoRefresh moves the data to a healthy block, thus preventing the controller from reading blocks with too many error bits and averting read disturbance and data corruption.
Dynamic Data Refresh
Dynamic Data Refresh
Runs automatically in the background to reduce the risk of read disturbance and sustain data integrity in seldom-accessed areas by sequentially scanning the user area flag record without affecting the read/write operation. The data that has been completely moved to another block will be read and compared with the source data to ensure data integrity
Auto-Read Calibration
Auto-Read Calibration
As program/erase (P/E) cycles increase, memory cells age and cause voltage shifts that lead to high bit error rates (BER) when predefined read thresholds are fixed. The Auto-Read Calibration (ARC) function reduces BER and enhances reliability by adjusting/calibrating the read thresholds. ARC is supported by the TLC LDPC controller.
End-to End Data Path Protection
End-to End Data Path Protection
Ensures error checking and correction as data moves from the host to the storage device controller and vice versa. By covering the entire data path, end-to-end protection guarantees integrity at any point during data transfer

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