Data Integrity (NAND-level)
Hardware-Based In-Flight-Data Power Loss Protection
Data-in-Flight Power Loss Protection
Introduction
ATP HW+MCU-Based PLP Technology: Breakthrough Double-Layer Protection for Superior Data Integrity
ATP Power Loss Protection: Combining Hardware and Microcontroller for the Ultimate Protection
Integrating hardware and microcontroller technology, ATP’s solution offers a double layer of protection to ensure that critical data in flight is protected during sudden power interruptions. This solution is comprised of:
• High-quality polymer tantalum capacitors that act as power reservoirs that supply enough power to safely complete the flushing of data from the volatile DRAM to the non-volatile NAND flash.
• Microcontroller unit (MCU). A power management IC (PMIC) and firmware‑programmable MCU allows the PLP array to perform intelligently in various temperatures, power glitches and power states. It constantly checks the power supply, and when a power loss or failure is detected, it signals the capacitors to supply the power required to complete the write operation and safely store the data.
The ATP solution protects both data and storage device by providing over input voltage protection, power-up inrush current suppression, input power noise de-glitch, fast power on-off control, and PLP capacitors over voltage protection With customization options available, the HW+MCU-based design allows PLP capabilities to be tailor-fitted according to unique customer requirements, application-specific needs, or use cases.
ATP HW+MCU-Based PLP Technology Benefits
• Uncompromised Data Integrity. Minimizes the risk of data loss or corruption by ensuring that the writing process is completed and the data in flight is safely stored to the SSD.
• Dynamic Power Supply Monitoring and Rapid Response. The MCU detects power failure and activates the capacitors immediately to provide backup power, enabling data to be written safely before total power loss occurs.
• Long-Term, Consistent Performance. ATP uses high-quality polymer tantalum capacitors for their high reliability and long lifecycle. They are ideal for applications where reliability and durability are paramount.
Features and Benefits of SSDs with HW+MCU-Based PLP Technology
| 1. Input Over Voltage Protection Input Reverse Voltage Protection |
Prevents high voltage and reverse voltage from damaging the SSD. | ||||||||
| 2. Irregular Power-Up Voltage | Powers up the SSD normally even if the input voltage is irregular. | ||||||||
| 3. Short Input Voltage Drop Detection & Debouncing |
Prevents the SSD from going offline when a weak Host is encountered in an application. [Note: A weak Host is one that is unable to maintain its voltage output for SSD stability while the SSD consumes larger current.] |
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| 4. PLP Capacitor Charging Monitor | (1) Prevents the PLP capacitor (CAP) from over charging, going out of specification charge voltage, which could damage the capacitor (2) Stops charging the CAP if a short circuit is detected. A short circuit will generate very high current flow and could damage the SSD circuit. |
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| 5. Very Short Power-Off-Then- Power-On Period Support | In traditional design, when a user powers off the SSD, the residual charge in the PLP CAP typically needs several seconds to discharge.The user should wait for some time before re-powering up the SSD. ATP SSDs with HW+MCU-based technology do not require long waits to power up the SSD again. | ||||||||
| 6. Precise Power-Up Sequence and System Reset Signal Control | Ensures stable and repeatable power-on sequence and reset signal control every time to power up the SSD successfully. | ||||||||
| 7. SSD Overheat Protection | The SSD will be turned off autonomously by the MCU while the over-heated condition is detected. Cache flushing will be performed before turning off the SSD. | ||||||||
| 8. PLP Life Reporting | Enables users to know the remaining lifespan of the PLP mechanism through the SMBus or SMART commands | ||||||||
| 9. SSD Power Consumption Reporting | Enables users to know SSD's power consumption in real-time through the SMBus of SMART commands. | ||||||||
| 10. NAND Flash Interface Signal Integrity Adjustment | Adjusts the NAND interface BIAS voltage, which is compensated by the device temperature, to improve the NAND bus signal integrity. | ||||||||
| 11. Hardware Status Reporting | Reports hardware abnormal conditions, such as PLP CAP under charged, PLP CAP over charged, unstable input voltage recorded, and more. This feature is used for conducting an initial investigation of the hardware circuit . | ||||||||
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